The package density of a semiconductor is continuously increased due to the increasing requirements for the miniaturization, light-weight and multifunction of electronic elements. Therefore, the package size and the area occupied by dies during packaging are desired to be reduced. In the technologies developed to satisfy the requirements mentioned above, the multi-die semiconductor packaging technology has a far-reaching contribution to the whole costs, efficiency and reliability of the packaged chips.
FIG. 1A to FIG. 1C illustrates a conventional method for manufacturing a multi-die package, as described in U.S. Pat. No. 6,674,173. As shown in FIG. 1A, a first die 100 with a plurality of first bond pads 106 disposed thereon is mounted faceup on a side of a die pad 104 of a lead frame 102, wherein the side of the first die 100 provided with the first bond pads 106 is a first substrate opposite side and the side opposite to the first substrate opposite side is a first substrate side. The first substrate side of the first die 100 is bound to the die pad 104 through a first binder layer 105. And the first bond pads 106 are electrically connected to lead wires 103 of the lead frame 102 respectively by using a plurality of first bond wires 108. Next, as shown in FIG. 1B, a second die 110 provided with a second bond pad 114 thereon is mounted facedown on another side of the die pad 104, wherein the side of the second die 110 provided with the first bond pad 106 thereon is the second base opposite side and the side opposite to the second base opposite side is the second base side. The second base side of the second die 110 is bound to the die pad 104 through a second binder layer 112. The second bond pad 114 is electrically connected to the lead wire 103 of the lead frame 102 by using a second bond wire 116. Since the second die 110 which is the same die type as the first die 100 has been mounted facedown, the internal wirings within the first die 100 and the second die 110 are asymmetrical. Accordingly, it is necessary to perform rewiring on the second die 110 so that the locations of the second bond pad 114 on the second die 110 are mirror symmetrical with the locations of the first bond pad 106 on the first die 100.
Finally, as shown in FIG. 1C, the first die 100, the second die 110 and the lead frame 102 are encapsulated by package paste 118 to form a package, in which only a portion of the lead wires 103 of the lead frame 102 are exposed.
In the prior art, the dies are bound on both sides of the lead frame in a pattern of single layer structure to form a multi-die semiconductor package. Since the dies on both sides of the lead frame are of the same die type mounted in different directions, the internal wirings within the dies disposed on both sides are asymmetrical. Accordingly, it is necessary that the die on one side is subjected to a further wiring process to form mirror symmetrical bond pads on the dies on both sides, which increases the complexity of the chip package process and thereby increases the costs.